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FEATURES +3 V, +5 V or 5 V Power Supplies Ultralow Power Dissipation (<0.5 W) Low Leakage (<100 pA) Low On Resistance (<50 ) Fast Switching Times Low Charge Injection TTL/CMOS Compatible 16-Lead DIP or SOIC Package
LC2MOS Precision 5 V/3 V Quad SPST Switches ADG511/ADG512/ADG513
FUNCTIONAL BLOCK DIAGRAMS
S1 IN1 D1 S2 IN2 IN2 D2 S3 IN3 D3 S4 IN4 D4 IN4 D4 D3 S4
IN4 D4
S1 IN1 D1 S2
IN2 IN1
S1 D1 S2 D2 S3 D3 S4
ADG511
IN3
ADG512
D2 S3
IN3
ADG513
APPLICATIONS Battery Powered Instruments Single Supply Systems Remote Powered Equipment +5 V Supply Systems Computer Peripherals such as Disk Drives Precision Instrumentation Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Sample Hold Systems Communication Systems Compatible with 5 V Supply DACs and ADCs such as AD7840/8, AD7870/1/2/4/5/6/8
SWITCHES SHOWN FOR A LOGIC "1" INPUT
The ADG511, ADG512 and ADG513 contain four independent SPST switches. The ADG511 and ADG512 differ only in that the digital control logic is inverted. The ADG511 switch is turned on with a logic low on the appropriate control input, while a logic high is required for the ADG512. The ADG513 contains two switches whose digital control logic is similar to that of the ADG511 while the logic is inverted in the remaining two switches.
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
The ADG511, ADG512 and ADG513 are monolithic CMOS ICs containing four independently selectable analog switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. These switch arrays are fabricated using Analog Devices' advanced linear compatible CMOS (LC2MOS) process which offers the additional benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. These features make the ADG511, ADG512 and ADG513 the optimum choice for a wide variety of signal switching tasks in precision analog signal processing and data acquisition systems. The ability to operate from single +3 V, +5 V or 5 V bipolar supplies make the ADG511, ADG512 and ADG513 perfect for use in battery-operated instruments, 4-20 mA loop systems and with the new generation of DACs and ADCs from Analog Devices. The use of 5 V supplies and reduced operating currents give much lower power dissipation than devices operating from 15 V supplies.
1. +5 Volt Single Supply Operation The ADG511/ADG512/ADG513 offers high performance, including low on resistance and wide signal range, fully specified and guaranteed with +3 V, 5 V as well as +5 V supply rails. 2. Ultralow Power Dissipation CMOS construction ensures ultralow power dissipation. 3. Low RON 4. Break-Before-Make Switching Switches are guaranteed to have break-before-make operation. This allows multiple outputs to be tied together for multiplexer applications without the possibility of momentary shorting between channels.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADG511/ADG512/ADG513-SPECIFICATIONS1
Dual Supply (V
Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS VDD VSS IDD ISS
DD
= +5 V
10%, VSS = -5 V
10%, GND = 0 V, unless otherwise noted)
T Versions -55 C to +25 C +125 C VDD to VSS 30 50 50 0.025 0.1 0.025 0.1 0.05 0.2
B Versions -40 C to +25 C +85 C VDD to VSS 30
Units V typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ pC typ dB typ dB typ pF typ pF typ pF typ
Test Conditions/Comments
VD = 3.5 V, IS = -10 mA; VDD = +4.5 V, VSS = -4.5 V VDD = +5.5 V, VSS = -5.5 V VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = VS = 4.5 V; Test Circuit 3
0.025 0.1 0.025 0.1 0.05 0.2
2.5 2.5 5 2.4 0.8
2.5 2.5 5 2.4 0.8
0.005
0.1
0.005
0.1
VIN = VINL or VINH
200 375 120 150 100 11 68 85 9 9 35 +4.5/5.5 -4.5/-5.5 0.0001 1 0.0001 1
200 375 120 150 100 11 68 85 9 9 35 +4.5/5.5 -4.5/-5.5 0.0001 1 0.0001 1
RL = 300 . CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 . CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = +3 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz
V min/max V min/max A typ A max A typ A max
VDD = +5.5 V, VSS = -5.5 V Digital Inputs = 0 V or 5 V
NOTES 1 Temperature ranges are as follows: B Versions -40C to +85C; T Versions -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. B
ADG511/ADG512/ADG513 Single Supply (V
Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS VDD IDD
DD
= +5 V
10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Versions -40 C to +25 C +85 C 0 V to VDD 45 75 0.025 0.1 0.025 0.1 0.05 0.2 0.025 0.1 0.025 0.1 0.05 0.2 45 75 T Versions -55 C to +25 C +125 C 0 V to VDD
Units V typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ pC typ dB typ dB typ pF typ pF typ pF typ
Test Conditions/Comments
VD = +3.5 V, IS = -10 mA; VDD = +4.5 V VDD = +5.5 V VD = 4.5/1 V, VS = 1 4.5 V; Test Circuit 2 VD = 4.5/1 V, VS = 1 4.5 V; Test Circuit 2 VD = VS = +4.5 V/+1 V; Test Circuit 3
2.5 2.5 5 2.4 0.8
2.5 2.5 5 2.4 0.8
0.005
0.1
0.005
0.1
VIN = VINL or VINH
250 500 50 100 200 16 68 85 9 9 35 +4.5/5.5 0.0001 1
250 500 50 100 200 16 68 85 9 9 35 +4.5/5.5 0.0001 1
RL = 300 , CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = +2 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz
V min/max A typ A max
VDD = +5.5 V Digital Inputs = 0 V or 5 V
NOTES 1 Temperature ranges are as follows: B Versions -40C to +85C; T Versions -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
REV. B
-3-
Single Supply (V
Parameter ANALOG SWITCH Analog Signal Range RON
ADG511/ADG512/ADG513-SPECIFICATIONS1
DD
= +3.3 V
10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Versions 0 C to +25 C +70 C 0 V to VDD 200 500
Units V typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ pC typ dB typ dB typ pF typ pF typ pF typ
Test Conditions/Comments
VD = +1.5 V, IS = -1 mA; VDD = +3 V VDD = +3.6 V VD = 2.6/1 V, VS = 1 2.6 V; Test Circuit 2 VD = 2.6/1 V, VS = 1 2.6 V; Test Circuit 2 VD = VS = +2.6 V/+1 V; Test Circuit 3
LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG513 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS VDD IDD
0.025 0.1 0.025 0.1 0.05 0.2
2.5 2.5 5 2.4 0.8
0.005
0.1
VIN = VINL or VINH
600 1200 100 160 500 11 68 85 9 9 35 3/3.6 0.0001 1
RL = 300 , CL = 35 pF; VS = +1 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = +1 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = +1 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz
V min/max A typ A max
VDD = +3.6 V Digital Inputs = 0 V or 3 V
NOTES 1 Temperature ranges are as follows: B Versions -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-4-
REV. B
ADG511/ADG512/ADG513
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V Analog, Digital Inputs2 . . . . . . . . . . . VSS -2 V to VDD + 2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . +300C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model1 ADG511BN ADG511BR ADG511ABR4 ADG511TQ4 ADG512BN ADG512BR ADG512ABR4 ADG512TQ4 ADG513BN ADG513BR ADG513ABR4
Temperature Range2 -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C
Package Option3 N-16 R-16A R-16A Q-16 N-16 R-16A R-16A Q-16 N-16 R-16A R-16A
NOTES 1 For availability of MIL-STD-883, Class B processed parts, contact factory. 2 3.3 V specifications apply over 0C to +70C temperature range. 3 N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip. 4 Trench isolated latch-up proof parts. See Trench Isolation section.
REV. B
-5-
ADG511/ADG512/ADG513
PIN CONFIGURATION (DIP/SOIC) TERMINOLOGY
IN1 1 D1 2 S1 3 VSS 4
16 IN2 15 D2
13 VDD TOP VIEW GND 5 (Not to Scale) 12 NC
ADG511 ADG512 ADG513
14 S2
S4 6 D4 7 IN4 8
11 S3 10 D3 9
IN3
NC = NO CONNECT
Truth Table (ADG511/ADG512)
ADG511 In 0 1
ADG512 In 1 0
Switch Condition ON OFF
Truth Table (ADG513)
Logic 0 1
Switch 1, 4 OFF ON
Switch 2, 3 ON OFF
Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to GND. GND Ground (0 V) reference. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. IN Logic control input. RON Ohmic resistance between D and S. IS (OFF) Source leakage current with the switch "OFF." ID (OFF) Drain leakage current with the switch "OFF." ID, IS (ON) Channel leakage current with the switch "ON." VD (VS) Analog voltage on terminals D, S. CS (OFF) "OFF" switch source capacitance. CD (OFF) "OFF" switch drain capacitance. CD, CS (ON) "ON" switch capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tD "OFF" or "ON" time measured between the 90% points of both switches when switching from one address state to another. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an "OFF" switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.
VDD VSS
-6-
REV. B
Typical Performance Graphs-ADG511/ADG512/ADG513
50 TA = +25 C 40
10mA VDD = +5V VSS = -5V 1mA
30
ISUPPLY
VDD = +3V VSS = -3V
100 A I-, I+ 10 A
RON -
20 VDD = +5V VSS = -5V
1A
10
1 SW 4 SW 100nA
0 -5
10nA
-4 0 -3 -2 -1 1 2 3 4 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 5
10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
Figure 1. On Resistance as a Function of VD (VS) Dual Supplies
Figure 4. Supply Current vs. Input Switching Frequency
50 VDD = +5V VSS = -5V 40
LEAKAGE CURRENT - nA
10 VDD = +5V VSS = -5V VS = 5V VD = 5V
ID (OFF)
1
30
RON -
+125 C +85 C 20 +25 C
0.1
ID (ON) 0.01 IS (OFF)
10
0 -5
-4
0 -3 -2 -1 1 2 3 4 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
5
0.001 25
35
45
55
65 75 85 95 TEMPERATURE - C
105
115
125
Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures
Figure 5. Leakage Currents as a Function of Temperature
90 TA = +25 C 80 70 60
RON -
120 VDD = +5V VSS = -5V
OFF ISOLATION - dB
VDD = +3V VSS = 0V
100
80
50 40 VDD = +5V VSS = 0V
60
30 20
40 100
0
1 2 3 4 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
5
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 3. On Resistance as a Function of VD (VS) Single Supply
Figure 6. Off Isolation vs. Frequency
REV. B
-7-
ADG511/ADG512/ADG513
0.008 VDD = +5V VSS = -5V TA = +25 C 0.004
LEAKAGE CURRENT - nA
ID (ON)
0.002
ID (OFF)
network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the 3 V input range. The acquisition time is 2.5 s while the settling time is 1.85 s.
+5V
0.000
IS (OFF) SW2 +5V S SW1 AD845 -5V -4 -3 -2 -1 1 2 3 4 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 5 S D D VIN
2200pF +5V
-0.002
-0.004
RC 75
CC 1000pF
OP07
VOUT
-0.006 -5
CH 2200pF
-5V
Figure 7. Leakage Currents as a Function of VD (VS)
ADG511 ADG512 ADG513
-5V 110 VDD = +5V VSS = -5V 100
Figure 9. Accurate Sample-and-Hold
TRENCH ISOLATION
90
80
The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 10). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of "latch-up" caused by parasitic junctions between CMOS transistors. Latch-up is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR)-type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up-proof circuit.
VS VG VD VS VG VD
CROSSTALK - dB
70
60 100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 8. Crosstalk vs. Frequency
APPLICATION
Figure 9 illustrates a precise sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG511/ADG512/ ADG513 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 15 V/s. A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differential effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation
T R E N C H
P+
P-CHANNEL
P+
N-
T R E N C H
N+
N-CHANNEL
N+
P-
T R E N C H
BURIED OXIDE LAYER SUBSTRATE (BACKGATE)
Figure 10. Trench Isolation
-8-
REV. B
ADG511/ADG512/ADG513 Test Circuits
IDS V1 IS (OFF) S VS D VS RON = V1/IDS A S D ID (OFF) A VD
VS ID (ON) S D A VD
1. On Resistance
2. Off Leakage
3. On Leakage
VDD 0.1 F 3V VDD S VS D RL 300 GND VSS VOUT CL 35pF VIN VIN ADG511 3V ADG512 50% 90% VOUT 50% 90% 50% 50%
IN
0.1 F VSS
tON
tOFF
4. Switching Times
VDD 0.1 F 3V VDD VS1 VS2 S1 S2 IN1, IN2 GND VSS D1 D2 RL2 300 VOUT2 CL2 35pF VOUT2 0V 0.1 F VSS 90% 90% RL1 300 CL1 35pF VOUT1 VOUT1 0V VIN 0V 50% 90% 50% 90%
VIN
tD
tD
5. Break-Before-Make Time Delay
VDD 3V VDD RS VS S D CL 10nF VOUT GND VSS VSS QINJ = CL VOUT VOUT VOUT VIN
IN
6. Charge Injection
REV. B
-9-
ADG511/ADG512/ADG513 Test Circuits (continued)
VDD VDD 0.1 F VDD VDD S D RL 50 VS VIN IN VOUT GND VSS RL 50 D GND S VSS CHANNEL TO CHANNEL CROSSTALK = 20 LOG VS/VOUT NC VOUT VS S D 50 0.1 F
VIN1 VIN2
0.1 F VSS
0.1 F VSS
7. Off Isolation
8. Channel-to-Channel Crosstalk
-10-
REV. B
ADG511/ADG512/ADG513
OUTLINE DIMENSIONS
Dimensions are shown in inches and (mm).
16-Lead Plastic DIP (N-16)
0.840 (21.34) 0.745 (18.92)
16 1 9 8
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
16-Lead Cerdip (Q-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
1
0.310 (7.87) 0.220 (5.59)
8
PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.100 (2.54) BSC
0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76)
15 0
0.015 (0.38) 0.008 (0.20)
16-Lead SOIC (R-16A)
0.3937 (10.00) 0.3859 (9.80)
16 1 9 8
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 SEATING (1.27) PLANE BSC
0.0192 (0.49) 0.0138 (0.35)
8 0.0099 (0.25) 0 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
REV. B
-11-
PRINTED IN U.S.A.
C1688b-0-10/99

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